Design of a reconfigurable FFT processor using multi-objective genetic algorithm

This paper describes the implementation of Multi-objective Genetic Algorithm (MOGA) in a 16-point Radix-4 Single Path Delay Feedback (R4SDF) pipelined Fast Fourier Transform (FFT) processor in Verilog. The role of MOGA is to optimize the wordlength of the FFT coefficient and at the same time make sure the processor operates at acceptable Signal to Noise Ratio (SNR). Reducing the wordlength of FFT coefficient will contribute to lower Switching Activity (SA), thus lower power consumption is required for the operation of FFT processor

Design high frequency surgical robot controller: design FPGA-based controller for surgical robot manipulator simscape modeling

Recent developments of robotics allocated many of industrial and medical activities. So that most of industries turned to use surgical robots in their production line or in their surgery. Being precise, spent less time-consuming, present uniform quality with less cost and reducing waste and energy are some advantages of using robots in industry. This paper has two important objectives: a) study on modeling and controlling of 4 degrees of freedom (DOF) based on Simscape software and b) design FPGA-based controller for this type of surgical robot manipulator. Simscape provides an environment for modeling and simulating physical systems. Simscape modeling can be designed to control and test system-level performance. Conventional PID controller is a stable linear type model-free controller that reduces the delay time in highly nonlinear system. In this research, linear controller need real time mobility operation, and one of the most important devices which can be used to solve this challenge is Field Programmable Gate Array (FPGA). FPGA can be used to design a controller in a single chip Integrated Circuit (IC). To design PID type FPGA-based controller two types algorithm are needed: derivative algorithm and integral algorithm. In HDL based derivative algorithm the minimum input arrival time before clock is 16.466 ns and the maximum frequency is 60.73 MHz, but in the best design action, the maximum frequency to design this single chip algorithm should be 63.629 MHz. In HDL integral algorithm the minimum input arrival time before clock is 15.599 ns and the maximum frequency is 64.1 MHz, but in the best design action, the maximum frequency to design this single chip algorithm should be 178.190 MHz

Robust controller design for single axis magnetic levitation system.

This paper demonstrates theoretically the main idea of magnetic force control in magnetic levitation system using flux density measurements. A Hall-effect sensor is used to sense the flux density in the air gap. The magnetic force is obtained by its proportional relation to the flux density. A simple magnetic levitation system which consists of a U-shaped electromagnet and a manipulator is used. First, the system dynamics are described in state space form using air gap displacement, velocity of the magnetically levitated manipulator, and the flux density as state variables. Second, the magnetic force regulated using Hf controller to achieve robust stability, disturbance/noise rejection and asymptotic tracking. Simulation results in terms of speed and accuracy are presented

Enhancement of DNA microarray images using mathematical morphological image processing

DNA microarray images contain spots that represent the gene expression of normal and cancer samples. As there are numerous spots on DNA microarray images, image processing can help in enhancing an image and assisting analysis. The mathematical morphology is proposed to enhance the microarray image and analyse noise removal on the image. This follows an experiment in which the erosion, dilation, opening, closing, white top-hat (WTH) and black top-hat (BTH) operations were applied on a DNA microarray image and its results analysed. Noise was completely removed by the erosion operation and the images were enhanced

Optimization of fast fourier transform processor using genetic algorithm on Raspberry Pi

In many areas of engineering and science are widely using FFT processors in most of their applications, thus, the modern science requires continuously new optimizations which includes the FFT processor to have a lower power consumption and a smaller size. This paper revolves around the 16-point Radix-4 Single Path Delay Feedback (R4SDF) for optimizing the pipelined Fast Fourier Transform (FFT) processor, which can be done by using both Single Objective Genetic Algorithm (SOGA) and Multi-Objective Genetic Algorithm (MOGA), Signal to Noise Ratio (SNR) value which depends on the word length of the FFT processor, higher word length value of the FFT processor will result in a higher value for the SNR, Thus, this research aims to reduce the power consumption of the FFT processor by lowering the word length of Twiddle Factor for the FFT by using a SOGA to find the optimum results for SNR values while MOGA is set to find the optimum values for both SNR and SA while lowering the Word Length. Over the years the Genetic Algorithms (GA) proved to be one of the best methods for optimization. In this research the GA is for reducing the word length by optimizing its coefficients. The required amount of value for the SNR is to be more than 63 dB and less than 192 for SA. The proposed work was done successfully in optimizing the FFT by using SOGA to lower the word length until 12 bits and obtaining a SNR value of 66.452 which resulted in an improvement of 5.47% for SNR while MOGA was achieve a value of 65.033dB which provides (3.22%) improvement for the SNR and SA value of 140 which made reduction by (27%) for the SA

Adaptive MIMO Fuzzy Compensate Fuzzy Sliding Mode Algorithm: Applied to Second Order Nonlinear System.

This research is focused on proposed adaptive fuzzy sliding mode algorithms with the adaptation laws derived in the Lyapunov sense. The stability of the closed-loop system is proved mathematically based on the Lyapunov method. Adaptive MIMO fuzzy compensate fuzzy sliding mode method design a MIMO fuzzy system to compensate for the model uncertainties of the system, and chattering also solved by linear saturation method. Since there is no tuning method to adjust the premise part of fuzzy rules so we presented a scheme to online tune consequence part of fuzzy rules. Classical sliding mode control is robust to control model uncertainties and external disturbances. A sliding mode method with a switching control low guarantees the stability of the certain and/or uncertain system, but the addition of the switching control low introduces chattering into the system. One way to reduce or eliminate chattering is to insert a boundary layer method inside of a boundary layer around the sliding surface. Classical sliding mode control method has difficulty in handling unstructured model uncertainties. One can overcome this problem by combining a sliding mode controller and artificial intelligence (e.g. fuzzy logic). To approximate a timevarying nonlinear dynamic system, a fuzzy system requires a large amount of fuzzy rule base. This large number of fuzzy rules will cause a high computation load. The addition of an adaptive law to a fuzzy sliding mode controller to online tune the parameters of the fuzzy rules in use will ensure a moderate computational load. The adaptive laws in this algorithm are designed based on the Lyapunov stability theorem. Asymptotic stability of the closed loop system is also proved in the sense of Lyapunov

Transistor sizing methodology for low noise charge sensitive amplifier with input transistor working in moderate inversion

In this paper noise contribution of current source transistors and sizing methodology in charge sensitive amplifier for application in the front-end readout electronics is presented. In modern deep-submicron technologies, MOS transistor operating region tends to shift from strong inversion to moderate inversion, this makes traditional square-law MOS device modeling not applicable anymore. Thus a simplified EKV model, which is quite successful in all CMOS operating regions, has been adopted to develop a new analytical methodology to optimize geometry of current source transistors so that the noise contribution from these transistors is only a fraction of input transistor noise. A charge sensitive amplifier based on dual PMOS cascode structure is designed by adopting this current source transistor sizing methodology, and has been simulated using 130nm CMOS technology. The proposed methodology and noise contribution from current source transistors have been found in good agreement with simulation results using deep-submicron CMOS technology

Development of power recovery circuit for bio-implantable stimulator

This paper presents a modified design of low power recovery circuit in micro-system implanted device to stimulate the human nerve and muscle. The amplitude shift keying ASK was used to modulate data by using operating frequency 6.78MHz ISM industrial scientific medical band to be less invasive to tissue. The proposed system consists of an external part which has ASK modulator and class-E power amplifier with 94.5% efficiency. The internal part has half wave rectifier and voltage regulator to generate very stable 1.8VDC using 0.35um CMOS technology. The Orcad pspice 16.6 and MULTISIM 11 software were used to simulate the design of power recovery and class-E power amplifier respectively. The regulated voltage utilised to power the sub-electronic device implanted inside human body with very stable voltage even change implanted load resistance. The proposed system has 12.5%modulation index and low power consumption

Low Cost front-end readout electronic for instrumentation used in Neutron experiments.

In the field of material characterization, the neutron scattering technique is found to be useful in so many applications. This technique requires a position sensitive neutron detector (PSND) and their front-end readouts (FER) electronic to detect the position of neutron interactions. Normally, the PSND is designed for specific applications and has unique technical specifications. Therefore, it requires a customised electronic FER to match its specifications. Furthermore, a large active area requires a large number of FER electronic and, therefore, there is, also, an increased development cost. This paper presents a simple and low-cost design for FER electronic which consists of an eight channels preamplifier-shaper suitable for instrumentation used in neutron experiments. This FER was built entirely with low-noise FET-input operational amplifier (Op-amp) and passive components. The development cost is around U.S. $50/channel. Results have shown that it is capable of accepting a wide dynamic range input charge (20 to 600 fC) with an excellent output linearity (nonlinearity < 1%). It has a good equivalent noise charge (ENC) with a performance average of 2113 e- and is less sensitive to input capacitance variation (24 e-/pF)

Genetic algorithm optimization for coefficient of FFT processor

This paper describes the implementation of Single-objective Genetic Algorithm (SOGA) and Multi-objectives Genetic Algorithm (MOGA) to optimize the pipelined Fast Fourier Transform (FFT) coefficient in order to improve the performance of Signal to Noise Ratio (SNR) and also the Switching Activity (SA). The SA and SNR are optimized separately in a Radix-4 Single Path Delay Feedback (R4SDF) pipelined Fast Fourier Transform (FFT) processor using SOGA. The MOGA optimized both objectives using Weighted-Sum approach